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| author | Andrew Waterman <andrew@sifive.com> | 2022-05-13 13:58:10 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-13 13:58:10 -0700 |
| commit | 78dfe62633ce4fe6e6a70afae04168e1f102b673 (patch) | |
| tree | 8a62f17aa8f261bc9ac8015cd28257da100727ab /riscv/processor.cc | |
| parent | ff645fb4eb9cd8a957dd8826369de8dd7e1fb8a3 (diff) | |
| download | spike-78dfe62633ce4fe6e6a70afae04168e1f102b673.zip spike-78dfe62633ce4fe6e6a70afae04168e1f102b673.tar.gz spike-78dfe62633ce4fe6e6a70afae04168e1f102b673.tar.bz2 | |
Fix disassembly of custom instructions that overlap standard ones (#999)
Iterate over the instruction chains in reverse order, prioritizing
the last call to `disassembler_t::add_insn`.
To preserve behavior for the standard instructions, reverse the order
in which we add instructions in the `disassembler_t` constructor.
Supersedes #995.
Diffstat (limited to 'riscv/processor.cc')
0 files changed, 0 insertions, 0 deletions