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| author | Chih-Min Chao <48193236+chihminchao@users.noreply.github.com> | 2022-04-07 14:03:50 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-04-06 23:03:50 -0700 |
| commit | 70b7e9ca2d04effda5fe964c968fbbabf72e54d9 (patch) | |
| tree | 374dcdb4c1a9225e244dc1fa3972195fcc51f852 /riscv/processor.cc | |
| parent | 1767a27ad4cf8f9eb1a30d9d9a2495477071339f (diff) | |
| download | spike-70b7e9ca2d04effda5fe964c968fbbabf72e54d9.zip spike-70b7e9ca2d04effda5fe964c968fbbabf72e54d9.tar.gz spike-70b7e9ca2d04effda5fe964c968fbbabf72e54d9.tar.bz2 | |
mmu: support asid/vmid (#928)
The change makes [v]satp.asid and hgatp.vmid writtable and supports
maximum length for rv32 and rv64. Software could write and read the
satp.asid to get the valid length or check if the core supports
asid/vmid or not. However, there is no official way to describe this hardware
capability (device tree or something else). Two implementation flags
are also added for future use and enabled by default.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index e6783bf..3313dfc 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -57,6 +57,9 @@ processor_t::processor_t(isa_parser_t isa, const char* varch, else if (isa.get_max_xlen() == 64) set_mmu_capability(IMPL_MMU_SV48); + set_impl(IMPL_MMU_ASID, true); + set_impl(IMPL_MMU_VMID, true); + reset(); } |