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authorScott Johnson <scott.johnson@arilinc.com>2021-11-13 09:17:10 -0800
committerScott Johnson <scott.johnson@arilinc.com>2021-11-13 09:17:10 -0800
commit5cf772f90a94bcbd2ed2191e6809bd14eee201cb (patch)
treeebe50e52170f65ce977545343f6f6e87699fb697 /riscv/processor.cc
parentdbf9fdd3a06694c53ce2e468f690736f60d8567b (diff)
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Use enum to specify the 3 options for masking of intr CSRs
Because using two booleans gives the impression that there are four possibilities. Since hideleg is itself masked by mideleg, there are effectively only three choices, so make that explicit via enum.
Diffstat (limited to 'riscv/processor.cc')
-rw-r--r--riscv/processor.cc12
1 files changed, 4 insertions, 8 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc
index aee457c..3b7de8f 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -399,8 +399,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
~MIP_HS_MASK, // read_mask
MIP_SSIP, // ip_write_mask
~MIP_HS_MASK, // ie_write_mask
- true, // mask_mideleg
- false, // mask_hideleg
+ generic_int_accessor_t::mask_mode_t::MIDELEG,
0 // shiftamt
);
@@ -409,8 +408,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
MIP_HS_MASK, // read_mask
MIP_VSSIP, // ip_write_mask
MIP_HS_MASK, // ie_write_mask
- true, // mask_mideleg
- false, // mask_hideleg
+ generic_int_accessor_t::mask_mode_t::MIDELEG,
0 // shiftamt
);
@@ -419,8 +417,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
MIP_VS_MASK, // read_mask
MIP_VS_MASK, // ip_write_mask
MIP_VS_MASK, // ie_write_mask
- false, // mask_mideleg
- false, // mask_hideleg
+ generic_int_accessor_t::mask_mode_t::NONE,
0 // shiftamt
);
@@ -429,8 +426,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
MIP_VS_MASK, // read_mask
MIP_VSSIP, // ip_write_mask
MIP_VS_MASK, // ie_write_mask
- false, // mask_mideleg
- true, // mask_hideleg
+ generic_int_accessor_t::mask_mode_t::HIDELEG,
1 // shiftamt
);