Fix tval on illegal instruction faults with long illegal instruction

The current spike implementation does not include the ILEN (maximum
instruction length supported by the implementation), which is required
to constrain the value of tval on an illegal instruction exception.

Consider an implementation supporting only an RV64I base instruction
set. The ILEN is 32 bits (spec sec. 1.5), and the MXLEN is 64 bits (spec
sec. 5.1). Under an illegal instruction exception with the instruction
longer than the ILEN, the mtval should contain the first ILEN (32 bits)
of the faulting instruction. However, the current spike implementation
lets the mtval be the instruction's first MXLEN (64 bits).

To fix this bug, this PR masks out the upper bits of the tval and leaves
the first ILEN bits of the faulting instruction. When this PR is being
made, all official instructions are either 16 or 32 bits. So, We hard-
code the ILEN to 32 bits.

1 files changed, 4 insertions, 1 deletions

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 620a6f4..3d56abc 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -949,7 +949,10 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek)
 
 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 {
-  throw trap_illegal_instruction(insn.bits());
+  // The illegal instruction can be longer than ILEN bits, where the tval will
+  // contain the first ILEN bits of the faulting instruction. We hard-code the
+  // ILEN to 32 bits since all official instructions have at most 32 bits.
+  throw trap_illegal_instruction(insn.bits() & 0xffffffffULL);
 }
 
 insn_func_t processor_t::decode_insn(insn_t insn)