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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-10 11:02:23 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-10 23:05:58 +0800 |
| commit | 2aaa89c0cf8fe0f45d284c0847f11d175eb82e03 (patch) | |
| tree | 82af2947eace87c64cb841ce5c8ca6d80c102f98 /riscv/processor.cc | |
| parent | 793ffe508a5b81ce27f1baf2c5afb0b58a4236c6 (diff) | |
| download | spike-2aaa89c0cf8fe0f45d284c0847f11d175eb82e03.zip spike-2aaa89c0cf8fe0f45d284c0847f11d175eb82e03.tar.gz spike-2aaa89c0cf8fe0f45d284c0847f11d175eb82e03.tar.bz2 | |
Improve write log for vtype in set_vl
Two writes to vtype will be logged in commitlog if vill is true
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 790f18c..620a6f4 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -512,7 +512,6 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT { int new_vlmul = 0; if (vtype->read() != newType) { - vtype->write_raw(newType); vsew = 1 << (extract64(newType, 3, 3) + 3); new_vlmul = int8_t(extract64(newType, 0, 3) << 5) >> 5; vflmul = new_vlmul >= 0 ? 1 << new_vlmul : 1.0 / (1 << -new_vlmul); @@ -527,6 +526,8 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT if (vill) { vlmax = 0; vtype->write_raw(UINT64_MAX << (p->get_xlen() - 1)); + } else { + vtype->write_raw(newType); } } |