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| author | Andrew Waterman <andrew@sifive.com> | 2022-04-07 13:36:49 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-04-07 13:36:49 -0700 |
| commit | 1ed910b229dcdafb25364053c1ed0bbb3fa81fcf (patch) | |
| tree | 13f4e0f4a94738c74765f83b35a660a78362474e /riscv/processor.cc | |
| parent | 70b7e9ca2d04effda5fe964c968fbbabf72e54d9 (diff) | |
| parent | dba7efaf9e2e8d5251820c8555a184f715bb4d46 (diff) | |
| download | spike-1ed910b229dcdafb25364053c1ed0bbb3fa81fcf.zip spike-1ed910b229dcdafb25364053c1ed0bbb3fa81fcf.tar.gz spike-1ed910b229dcdafb25364053c1ed0bbb3fa81fcf.tar.bz2 | |
Merge pull request #966 from riscv-software-src/fix-riscv-build
Rename processor_t::set_csr to put_csr to fix build on RISC-V
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 3313dfc..8e2374d 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -499,8 +499,8 @@ void processor_t::reset() if (n_pmp > 0) { // For backwards compatibility with software that is unaware of PMP, // initialize PMP to permit unprivileged access to all of memory. - set_csr(CSR_PMPADDR0, ~reg_t(0)); - set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT); + put_csr(CSR_PMPADDR0, ~reg_t(0)); + put_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT); } for (auto e : custom_extensions) // reset any extensions @@ -841,7 +841,7 @@ int processor_t::paddr_bits() return max_xlen == 64 ? 50 : 34; } -void processor_t::set_csr(int which, reg_t val) +void processor_t::put_csr(int which, reg_t val) { val = zext_xlen(val); auto search = state.csrmap.find(which); |