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| author | Andrew Waterman <andrew@sifive.com> | 2022-05-12 14:05:37 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-05-12 14:05:37 -0700 |
| commit | 11f5942b7d8211e61b5ad9259d118033692c0759 (patch) | |
| tree | 74ed9727e22bc5ec8786dd2d4a84ccb756234b59 /riscv/processor.cc | |
| parent | 615de147a26d1e342642848cc22c845853f5e11f (diff) | |
| download | spike-11f5942b7d8211e61b5ad9259d118033692c0759.zip spike-11f5942b7d8211e61b5ad9259d118033692c0759.tar.gz spike-11f5942b7d8211e61b5ad9259d118033692c0759.tar.bz2 | |
Don't register instructions that aren't supported
These add to the length of the instruction list without providing
an apparent benefit.
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 9ce9287..dd61cae 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -959,14 +959,16 @@ void processor_t::register_base_instructions() extern reg_t rv64i_##name(processor_t*, insn_t, reg_t); \ extern reg_t rv32e_##name(processor_t*, insn_t, reg_t); \ extern reg_t rv64e_##name(processor_t*, insn_t, reg_t); \ - register_insn((insn_desc_t) { \ - name##_supported, \ - name##_match, \ - name##_mask, \ - rv32i_##name, \ - rv64i_##name, \ - rv32e_##name, \ - rv64e_##name}); + if (name##_supported) { \ + register_insn((insn_desc_t) { \ + name##_supported, \ + name##_match, \ + name##_mask, \ + rv32i_##name, \ + rv64i_##name, \ + rv32e_##name, \ + rv64e_##name}); \ + } #include "insn_list.h" #undef DEFINE_INSN |