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| author | Andrew Waterman <andrew@sifive.com> | 2022-05-12 14:18:02 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-05-12 14:22:50 -0700 |
| commit | 0676421e93180f4e2421fb5058f5e6c1de8ae2c1 (patch) | |
| tree | 46555df9be250000df37fd430fee94b34006d79a /riscv/processor.cc | |
| parent | 68b20a9b8af4e9adbff9cccaef2b7c6b2c8ec190 (diff) | |
| download | spike-0676421e93180f4e2421fb5058f5e6c1de8ae2c1.zip spike-0676421e93180f4e2421fb5058f5e6c1de8ae2c1.tar.gz spike-0676421e93180f4e2421fb5058f5e6c1de8ae2c1.tar.bz2 | |
Assert that nullptrs can't make their way into the instructions list
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 2cc1003..98ae637 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -907,6 +907,8 @@ insn_func_t processor_t::decode_insn(insn_t insn) void processor_t::register_insn(insn_desc_t desc) { + assert(desc.rv32i && desc.rv64i && desc.rv32e && desc.rv64e); + instructions.push_back(desc); } |