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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-18 19:22:08 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-18 19:22:08 -0700 |
| commit | e638446bd99d5051b1d5a45dd38dab654b153f6a (patch) | |
| tree | 28a909929cdd274a46a3c316659c36cba8a5cbae /riscv/processor.cc | |
| parent | 787450f4d9b453ce89c871b3b380706d701c909a (diff) | |
| download | spike-e638446bd99d5051b1d5a45dd38dab654b153f6a.zip spike-e638446bd99d5051b1d5a45dd38dab654b153f6a.tar.gz spike-e638446bd99d5051b1d5a45dd38dab654b153f6a.tar.bz2 | |
clean up SR_EA, the enable accelerator bit in status reg
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index ac5c1f7..3fe0d99 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -210,9 +210,8 @@ reg_t processor_t::set_pcr(int which, reg_t val) #ifndef RISCV_ENABLE_FPU state.sr &= ~SR_EF; #endif -#ifndef RISCV_ENABLE_VEC - state.sr &= ~SR_EV; -#endif + if (!ext) + state.sr &= ~SR_EA; state.sr &= ~SR_ZERO; mmu->flush_tlb(); break; |