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author | Andrew Waterman <andrew@sifive.com> | 2022-10-19 21:24:23 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-10-19 21:34:25 -0700 |
commit | d41af9f81cb393ed6fad8b9cb756a5b459e7c9ab (patch) | |
tree | cbcbf16cef050f44dd8a7d0992878ee142e6f0b0 /riscv/mmu.h | |
parent | 8d40946475d73ce2627549b1857991d70cb1186b (diff) | |
download | spike-d41af9f81cb393ed6fad8b9cb756a5b459e7c9ab.zip spike-d41af9f81cb393ed6fad8b9cb756a5b459e7c9ab.tar.gz spike-d41af9f81cb393ed6fad8b9cb756a5b459e7c9ab.tar.bz2 |
Template-ize loads
Diffstat (limited to 'riscv/mmu.h')
-rw-r--r-- | riscv/mmu.h | 18 |
1 files changed, 1 insertions, 17 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index edf3d20..22edd6f 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -94,22 +94,6 @@ public: return load<T>(addr, RISCV_XLATE_VIRT|RISCV_XLATE_VIRT_HLVX); } - // template for functions that load an aligned value from memory - #define load_func(type, prefix, xlate_flags) \ - type##_t ALWAYS_INLINE prefix##_##type(reg_t addr) { return load<type##_t>(addr, xlate_flags); } - - // load value from memory at aligned address; zero extend to register width - load_func(uint8, load, 0) - load_func(uint16, load, 0) - load_func(uint32, load, 0) - load_func(uint64, load, 0) - - // load value from memory at aligned address; sign extend to register width - load_func(int8, load, 0) - load_func(int16, load, 0) - load_func(int32, load, 0) - load_func(int64, load, 0) - #ifndef RISCV_ENABLE_COMMITLOG # define WRITE_MEM(addr, value, size) ((void)(addr), (void)(value), (void)(size)) #else @@ -185,7 +169,7 @@ public: if (unlikely(addr & (sizeof(float128_t)-1))) throw trap_load_address_misaligned((proc) ? proc->state.v : false, addr, 0, 0); #endif - return (float128_t){load_uint64(addr), load_uint64(addr + 8)}; + return (float128_t){load<uint64_t>(addr), load<uint64_t>(addr + 8)}; } // store value to memory at aligned address |