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| author | Jerry Zhao <jerryz123@berkeley.edu> | 2022-12-29 15:26:16 -0800 |
|---|---|---|
| committer | Jerry Zhao <jerryz123@berkeley.edu> | 2023-01-03 10:09:20 -0800 |
| commit | c91fe0b0a628ac1050e2e024650484d8975b9a20 (patch) | |
| tree | d618e6d16ee1152286517ae3f75fab544a3a49fb /riscv/mmu.h | |
| parent | 0d13d07a045e546800f28c16937a85b6dec4178f (diff) | |
| download | spike-c91fe0b0a628ac1050e2e024650484d8975b9a20.zip spike-c91fe0b0a628ac1050e2e024650484d8975b9a20.tar.gz spike-c91fe0b0a628ac1050e2e024650484d8975b9a20.tar.bz2 | |
Add method to probe which memory regions are reservable
Default reservable regions is the same as before
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 8789c8c..723b08e 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -163,7 +163,7 @@ public: void clean_inval(reg_t addr, bool clean, bool inval) { convert_load_traps_to_store_traps({ const reg_t paddr = translate(addr, blocksz, LOAD, 0) & ~(blocksz - 1); - if (sim->addr_to_mem(paddr)) { + if (sim->reservable(paddr)) { if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD)) tracer.clean_invalidate(paddr, blocksz, clean, inval); } else { @@ -185,10 +185,10 @@ public: } reg_t paddr = translate(vaddr, 1, STORE, 0); - if (sim->addr_to_mem(paddr)) + if (sim->reservable(paddr)) return load_reservation_address == paddr; else - throw trap_store_access_fault((proc) ? proc->state.v : false, vaddr, 0, 0); // disallow SC to I/O space + throw trap_store_access_fault((proc) ? proc->state.v : false, vaddr, 0, 0); } template<typename T> |