Don't issue misaligned or non-power-of-2 MMIO accesses

@aswaterman explains:

Rather than requiring each MMIO device to support arbitrary sizes and
alignments, decompose MMIO misaligned loads and stores in such a way
as to guarantee their constituent parts are always aligned.
(Specifically, they now always decompose to a sequence of one-byte
accesses.)

This is not a semantic change for main-memory accesses, but it is a
semantic change for I/O devices.  It makes them more realistic, in that
most bus standards don't support non-power-of-2-sized accesses.

1 files changed, 1 insertions, 0 deletions

diff --git a/riscv/mmu.h b/riscv/mmu.h
index 6cf696b..56789e0 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -339,6 +339,7 @@ private:
   bool mmio_fetch(reg_t paddr, size_t len, uint8_t* bytes);
   bool mmio_load(reg_t paddr, size_t len, uint8_t* bytes);
   bool mmio_store(reg_t paddr, size_t len, const uint8_t* bytes);
+  bool mmio(reg_t paddr, size_t len, uint8_t* bytes, access_type type);
   bool mmio_ok(reg_t paddr, access_type type);
   void check_triggers(triggers::operation_t operation, reg_t address, std::optional<reg_t> data = std::nullopt);
   reg_t translate(reg_t addr, reg_t len, access_type type, uint32_t xlate_flags);