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| author | YenHaoChen <howard25336284@gmail.com> | 2023-06-09 09:28:15 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2023-06-12 09:13:08 +0800 |
| commit | 03b47351e69ae954e5b078e18cc10bf21df4712c (patch) | |
| tree | 1254e8bae9a661e2338e25d2088fd516684886c6 /riscv/mmu.h | |
| parent | 8780656d5aed11a9102bde440e3d9434bae28b7d (diff) | |
| download | spike-03b47351e69ae954e5b078e18cc10bf21df4712c.zip spike-03b47351e69ae954e5b078e18cc10bf21df4712c.tar.gz spike-03b47351e69ae954e5b078e18cc10bf21df4712c.tar.bz2 | |
Fix PMP checking region of cache-block management instructions
The spec says "The PMP access control bits shall be the same for all
physical addresses in the cache block [... else] the behavior of a CBO
instruction is UNSPECIFIED."
Thus, we only need to check the byte rs1 points to
(instead of the entire cache block).
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 5a4835c..efc6e9d 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -214,7 +214,7 @@ public: void clean_inval(reg_t addr, bool clean, bool inval) { convert_load_traps_to_store_traps({ - const reg_t paddr = translate(generate_access_info(addr, LOAD, {false, false, false}), blocksz) & ~(blocksz - 1); + const reg_t paddr = translate(generate_access_info(addr, LOAD, {false, false, false}), 1); if (sim->reservable(paddr)) { if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD)) tracer.clean_invalidate(paddr, blocksz, clean, inval); |