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authorMarcus Comstedt <marcus@mc.pp.se>2019-08-18 16:03:43 +0200
committerChih-Min Chao <chihmin.chao@sifive.com>2019-10-29 03:33:45 -0700
commit65648669c15343cb1aa6b102cf2eae0ed91024cd (patch)
tree4530bee628e72cf17adeca999e9826ea4a0f88a9 /riscv/mmu.cc
parent7c85cc44d13547ab7260438d97671d7f423e5d6c (diff)
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Implement support for big-endian hosts
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/mmu.cc')
-rw-r--r--riscv/mmu.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index a0e500b..eca090f 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -288,7 +288,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode)
if (!ppte || !pmp_ok(pte_paddr, vm.ptesize, LOAD, PRV_S))
throw_access_exception(addr, type);
- reg_t pte = vm.ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
+ reg_t pte = vm.ptesize == 4 ? from_le(*(uint32_t*)ppte) : from_le(*(uint64_t*)ppte);
reg_t ppn = pte >> PTE_PPN_SHIFT;
if (PTE_TABLE(pte)) { // next level of page table
@@ -310,7 +310,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode)
if ((pte & ad) != ad) {
if (!pmp_ok(pte_paddr, vm.ptesize, STORE, PRV_S))
throw_access_exception(addr, type);
- *(uint32_t*)ppte |= ad;
+ *(uint32_t*)ppte |= to_le((uint32_t)ad);
}
#else
// take exception if access or possibly dirty bit is not set.