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authorAndrew Waterman <andrew@sifive.com>2018-11-06 15:41:34 -0800
committerAndrew Waterman <andrew@sifive.com>2018-11-06 15:41:34 -0800
commit01252686902fa30665fbecfc1476d169ad1333d1 (patch)
tree4bc6765f43fc2626f00b986468e2a4bfe4dedde7 /riscv/insns
parent120d2975b3c58b98b4faaa5679bea677565d49f4 (diff)
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Report misaligned-address exception on failed store-conditionals
Previously, the exception would only be raised if the store-conditional would have succeeded.
Diffstat (limited to 'riscv/insns')
-rw-r--r--riscv/insns/sc_d.h11
-rw-r--r--riscv/insns/sc_w.h11
2 files changed, 8 insertions, 14 deletions
diff --git a/riscv/insns/sc_d.h b/riscv/insns/sc_d.h
index aeeabd3..f44d873 100644
--- a/riscv/insns/sc_d.h
+++ b/riscv/insns/sc_d.h
@@ -1,11 +1,8 @@
require_extension('A');
require_rv64;
-if (MMU.check_load_reservation(RS1))
-{
- MMU.store_uint64(RS1, RS2);
- WRITE_RD(0);
-}
-else
- WRITE_RD(1);
+bool have_reservation = MMU.check_load_reservation(RS1);
+MMU.amo_uint64(RS1, [&](uint64_t lhs) { return have_reservation ? RS2 : lhs; });
MMU.yield_load_reservation();
+
+WRITE_RD(!have_reservation);
diff --git a/riscv/insns/sc_w.h b/riscv/insns/sc_w.h
index 4b4be50..fe4fcdc 100644
--- a/riscv/insns/sc_w.h
+++ b/riscv/insns/sc_w.h
@@ -1,10 +1,7 @@
require_extension('A');
-if (MMU.check_load_reservation(RS1))
-{
- MMU.store_uint32(RS1, RS2);
- WRITE_RD(0);
-}
-else
- WRITE_RD(1);
+bool have_reservation = MMU.check_load_reservation(RS1);
+MMU.amo_uint32(RS1, [&](uint32_t lhs) { return have_reservation ? RS2 : lhs; });
MMU.yield_load_reservation();
+
+WRITE_RD(!have_reservation);