From 01252686902fa30665fbecfc1476d169ad1333d1 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 6 Nov 2018 15:41:34 -0800 Subject: Report misaligned-address exception on failed store-conditionals Previously, the exception would only be raised if the store-conditional would have succeeded. --- riscv/insns/sc_d.h | 11 ++++------- riscv/insns/sc_w.h | 11 ++++------- 2 files changed, 8 insertions(+), 14 deletions(-) (limited to 'riscv/insns') diff --git a/riscv/insns/sc_d.h b/riscv/insns/sc_d.h index aeeabd3..f44d873 100644 --- a/riscv/insns/sc_d.h +++ b/riscv/insns/sc_d.h @@ -1,11 +1,8 @@ require_extension('A'); require_rv64; -if (MMU.check_load_reservation(RS1)) -{ - MMU.store_uint64(RS1, RS2); - WRITE_RD(0); -} -else - WRITE_RD(1); +bool have_reservation = MMU.check_load_reservation(RS1); +MMU.amo_uint64(RS1, [&](uint64_t lhs) { return have_reservation ? RS2 : lhs; }); MMU.yield_load_reservation(); + +WRITE_RD(!have_reservation); diff --git a/riscv/insns/sc_w.h b/riscv/insns/sc_w.h index 4b4be50..fe4fcdc 100644 --- a/riscv/insns/sc_w.h +++ b/riscv/insns/sc_w.h @@ -1,10 +1,7 @@ require_extension('A'); -if (MMU.check_load_reservation(RS1)) -{ - MMU.store_uint32(RS1, RS2); - WRITE_RD(0); -} -else - WRITE_RD(1); +bool have_reservation = MMU.check_load_reservation(RS1); +MMU.amo_uint32(RS1, [&](uint32_t lhs) { return have_reservation ? RS2 : lhs; }); MMU.yield_load_reservation(); + +WRITE_RD(!have_reservation); -- cgit v1.1