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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-06-06 03:24:52 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-06-18 08:56:11 -0700 |
commit | 80ebc70e43e48c5a851348e898c13a2d8a8148d7 (patch) | |
tree | a11e7fa87d5c71ea23b4c410cd2c26e7855dcce6 /riscv/insns/vsuxe_v.h | |
parent | 655aedc0ebd2326d69d389bc714c2d622bf2cb08 (diff) | |
download | spike-80ebc70e43e48c5a851348e898c13a2d8a8148d7.zip spike-80ebc70e43e48c5a851348e898c13a2d8a8148d7.tar.gz spike-80ebc70e43e48c5a851348e898c13a2d8a8148d7.tar.bz2 |
rvv: add load/store instructions
based on v-spec 0.7.1, support
section: 7
element size: 8/16/32/64
Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
Signed-off-by: Zakk Chen <zakk.chen@sifive.com>
Diffstat (limited to 'riscv/insns/vsuxe_v.h')
-rw-r--r-- | riscv/insns/vsuxe_v.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/riscv/insns/vsuxe_v.h b/riscv/insns/vsuxe_v.h new file mode 100644 index 0000000..940d8ad --- /dev/null +++ b/riscv/insns/vsuxe_v.h @@ -0,0 +1,38 @@ +// vsxe.v and vsxseg[2-8]e.v +const reg_t sew = P.VU.vsew; +const reg_t vl = P.VU.vl; +require(sew >= e8 && sew <= e64); +reg_t baseAddr = RS1; +reg_t stride = insn.rs2(); +reg_t vs3 = insn.rd(); +reg_t vlmax = P.VU.vlmax; +VI_DUPLICATE_VREG(stride, vlmax); +for (reg_t i = 0; i < vlmax && vl != 0; ++i) { + bool is_valid = true; + VI_ELEMENT_SKIP(i); + VI_STRIP(i) + + switch (sew) { + case e8: + if (is_valid) + MMU.store_uint8(baseAddr + index[i], + P.VU.elt<uint8_t>(vs3, vreg_inx)); + break; + case e16: + if (is_valid) + MMU.store_uint16(baseAddr + index[i], + P.VU.elt<uint16_t>(vs3, vreg_inx)); + break; + case e32: + if (is_valid) + MMU.store_uint32(baseAddr + index[i], + P.VU.elt<uint32_t>(vs3, vreg_inx)); + break; + case e64: + if (is_valid) + MMU.store_uint64(baseAddr + index[i], + P.VU.elt<uint64_t>(vs3, vreg_inx)); + break; + } +} +P.VU.vstart = 0; |