From 80ebc70e43e48c5a851348e898c13a2d8a8148d7 Mon Sep 17 00:00:00 2001
From: Chih-Min Chao <chihmin.chao@sifive.com>
Date: Thu, 6 Jun 2019 03:24:52 -0700
Subject: rvv: add load/store instructions

based on v-spec 0.7.1, support
  section: 7
  element size: 8/16/32/64

Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
Signed-off-by: Zakk Chen <zakk.chen@sifive.com>
---
 riscv/insns/vsuxe_v.h | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 riscv/insns/vsuxe_v.h

(limited to 'riscv/insns/vsuxe_v.h')

diff --git a/riscv/insns/vsuxe_v.h b/riscv/insns/vsuxe_v.h
new file mode 100644
index 0000000..940d8ad
--- /dev/null
+++ b/riscv/insns/vsuxe_v.h
@@ -0,0 +1,38 @@
+// vsxe.v and vsxseg[2-8]e.v
+const reg_t sew = P.VU.vsew;
+const reg_t vl = P.VU.vl;
+require(sew >= e8 && sew <= e64);
+reg_t baseAddr = RS1;
+reg_t stride = insn.rs2();
+reg_t vs3 = insn.rd();
+reg_t vlmax = P.VU.vlmax;
+VI_DUPLICATE_VREG(stride, vlmax);
+for (reg_t i = 0; i < vlmax && vl != 0; ++i) {
+  bool is_valid = true;
+  VI_ELEMENT_SKIP(i);
+  VI_STRIP(i)
+
+  switch (sew) {
+  case e8:
+    if (is_valid)
+      MMU.store_uint8(baseAddr + index[i],
+                      P.VU.elt<uint8_t>(vs3, vreg_inx));
+    break;
+  case e16:
+    if (is_valid)
+      MMU.store_uint16(baseAddr + index[i],
+                       P.VU.elt<uint16_t>(vs3, vreg_inx));
+    break;
+  case e32:
+    if (is_valid)
+      MMU.store_uint32(baseAddr + index[i],
+                       P.VU.elt<uint32_t>(vs3, vreg_inx));
+    break;
+  case e64:
+    if (is_valid)
+      MMU.store_uint64(baseAddr + index[i],
+                       P.VU.elt<uint64_t>(vs3, vreg_inx));
+    break;
+  }
+}
+P.VU.vstart = 0;
-- 
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