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authorAndrew Waterman <andrew@sifive.com>2022-10-17 13:51:59 -0700
committerAndrew Waterman <andrew@sifive.com>2022-10-17 13:51:59 -0700
commit68aeeb5500521ff52c216862f9a653b64191f3ad (patch)
tree407230ff48f79f177a792451598d9b2b6e3d34a0 /riscv/insns/vsmul_vx.h
parent191634d2854dfed448fc323195f9b65c305e2d77 (diff)
parent03be4ae6c7b8e9865083b61427ff9724c7706fcf (diff)
downloadspike-plic_uart_v1.zip
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Merge branch 'master' into plic_uart_v1plic_uart_v1
Diffstat (limited to 'riscv/insns/vsmul_vx.h')
-rw-r--r--riscv/insns/vsmul_vx.h9
1 files changed, 0 insertions, 9 deletions
diff --git a/riscv/insns/vsmul_vx.h b/riscv/insns/vsmul_vx.h
index 2e25670..d2724ee 100644
--- a/riscv/insns/vsmul_vx.h
+++ b/riscv/insns/vsmul_vx.h
@@ -2,20 +2,11 @@
VRM xrm = P.VU.get_vround_mode();
int64_t int_max = INT64_MAX >> (64 - P.VU.vsew);
int64_t int_min = INT64_MIN >> (64 - P.VU.vsew);
-int64_t sign_mask = uint64_t(1) << (P.VU.vsew - 1);
VI_VX_LOOP
({
- int64_t rs1_sign;
- int64_t vs2_sign;
- int64_t result_sign;
-
- rs1_sign = rs1 & sign_mask;
- vs2_sign = vs2 & sign_mask;
bool overflow = rs1 == vs2 && rs1 == int_min;
-
int128_t result = (int128_t)rs1 * (int128_t)vs2;
- result_sign = (rs1_sign ^ vs2_sign) & sign_mask;
// rounding
INT_ROUNDING(result, xrm, sew - 1);