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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-27 00:42:12 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-28 22:36:14 -0700 |
| commit | d4f881d0ecce46c6f011603aeb74ad3a72b28fbf (patch) | |
| tree | 1b28dbd6172bc8e9b87c4652890b4e101e95e67a /riscv/insns/vsetvl.h | |
| parent | 92d41ccbc02ed848d89ae4ed61be42730aa02140 (diff) | |
| download | spike-d4f881d0ecce46c6f011603aeb74ad3a72b28fbf.zip spike-d4f881d0ecce46c6f011603aeb74ad3a72b28fbf.tar.gz spike-d4f881d0ecce46c6f011603aeb74ad3a72b28fbf.tar.bz2 | |
rvv: wrap align and overlap checking macro
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vsetvl.h')
| -rw-r--r-- | riscv/insns/vsetvl.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vsetvl.h b/riscv/insns/vsetvl.h index fb3a558..4d03542 100644 --- a/riscv/insns/vsetvl.h +++ b/riscv/insns/vsetvl.h @@ -1,2 +1,2 @@ -require_vector_for_vsetvl; +require_vector_novtype(false); WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, RS2)); |