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| author | Andrew Waterman <andrew@sifive.com> | 2019-07-19 01:41:18 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-19 01:41:18 -0700 |
| commit | c4f61cafe2afd53781bc23138b1424430974808f (patch) | |
| tree | db781a09726809598000717943601c098920646e /riscv/insns/vsetvl.h | |
| parent | de967334ef8d7044f4de5ff521398342127404e7 (diff) | |
| download | spike-c4f61cafe2afd53781bc23138b1424430974808f.zip spike-c4f61cafe2afd53781bc23138b1424430974808f.tar.gz spike-c4f61cafe2afd53781bc23138b1424430974808f.tar.bz2 | |
Check vtype.vill for all vector instructions except vsetvl[i]
Diffstat (limited to 'riscv/insns/vsetvl.h')
| -rw-r--r-- | riscv/insns/vsetvl.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/insns/vsetvl.h b/riscv/insns/vsetvl.h index 773b984..4b1f2e8 100644 --- a/riscv/insns/vsetvl.h +++ b/riscv/insns/vsetvl.h @@ -1 +1,2 @@ +require_vector_for_vsetvl; WRITE_RD(P.VU.set_vl(insn.rs1(), RS1, RS2)); |