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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-08-03 01:25:53 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-08-03 21:53:16 -0700 |
| commit | 6e4977abdbe16dc7923a709cf3b3defb871c9061 (patch) | |
| tree | 579ac656ad7c3aceef1265004ef9e094c9937074 /riscv/insns/vsetvl.h | |
| parent | 959700ec11d5c5e8417533e6cddfada1a83c4770 (diff) | |
| download | spike-6e4977abdbe16dc7923a709cf3b3defb871c9061.zip spike-6e4977abdbe16dc7923a709cf3b3defb871c9061.tar.gz spike-6e4977abdbe16dc7923a709cf3b3defb871c9061.tar.bz2 | |
rvv: add 'vstartalu" option to --varch arugment
except for load/store instructions
0 : all instruction can't have non-zero vstart
not 0 : all instruction can have non-zero vstart if it is not required
vstart must be zero in spec
the default value is 1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vsetvl.h')
| -rw-r--r-- | riscv/insns/vsetvl.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vsetvl.h b/riscv/insns/vsetvl.h index 4d03542..2969edc 100644 --- a/riscv/insns/vsetvl.h +++ b/riscv/insns/vsetvl.h @@ -1,2 +1,2 @@ -require_vector_novtype(false); +require_vector_novtype(false, false); WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, RS2)); |