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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-25 22:46:48 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-12-20 09:58:46 -0800 |
| commit | 171cfe6bd144021c3218f0bb52ba0d632c38c509 (patch) | |
| tree | 0a11e8004acea26c65e79c8df272108c42d4903a /riscv/insns/vsetvl.h | |
| parent | 1c28009cfac464ac86ff5aea796297cc42e5f881 (diff) | |
| download | spike-171cfe6bd144021c3218f0bb52ba0d632c38c509.zip spike-171cfe6bd144021c3218f0bb52ba0d632c38c509.tar.gz spike-171cfe6bd144021c3218f0bb52ba0d632c38c509.tar.bz2 | |
rvv: change vsetvl[i] to match 0.8 spec
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vsetvl.h')
| -rw-r--r-- | riscv/insns/vsetvl.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vsetvl.h b/riscv/insns/vsetvl.h index 4b1f2e8..fb3a558 100644 --- a/riscv/insns/vsetvl.h +++ b/riscv/insns/vsetvl.h @@ -1,2 +1,2 @@ require_vector_for_vsetvl; -WRITE_RD(P.VU.set_vl(insn.rs1(), RS1, RS2)); +WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, RS2)); |