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| author | Andrew Waterman <andrew@sifive.com> | 2019-07-19 01:41:18 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-19 01:41:18 -0700 |
| commit | c4f61cafe2afd53781bc23138b1424430974808f (patch) | |
| tree | db781a09726809598000717943601c098920646e /riscv/insns/vrgather_vx.h | |
| parent | de967334ef8d7044f4de5ff521398342127404e7 (diff) | |
| download | spike-c4f61cafe2afd53781bc23138b1424430974808f.zip spike-c4f61cafe2afd53781bc23138b1424430974808f.tar.gz spike-c4f61cafe2afd53781bc23138b1424430974808f.tar.bz2 | |
Check vtype.vill for all vector instructions except vsetvl[i]
Diffstat (limited to 'riscv/insns/vrgather_vx.h')
| -rw-r--r-- | riscv/insns/vrgather_vx.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vrgather_vx.h b/riscv/insns/vrgather_vx.h index d6c2e38..e9ff3b1 100644 --- a/riscv/insns/vrgather_vx.h +++ b/riscv/insns/vrgather_vx.h @@ -1,6 +1,6 @@ // vrgather.vx vd, vs2, rs1, vm # vd[i] = (rs1 >= VLMAX) ? 0 : vs2[rs1]; require(P.VU.vsew >= e8 && P.VU.vsew <= e64); -require(!P.VU.vill); +require_vector; reg_t vl = P.VU.vl; reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); |