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author | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
commit | 68aeeb5500521ff52c216862f9a653b64191f3ad (patch) | |
tree | 407230ff48f79f177a792451598d9b2b6e3d34a0 /riscv/insns/vrgather_vi.h | |
parent | 191634d2854dfed448fc323195f9b65c305e2d77 (diff) | |
parent | 03be4ae6c7b8e9865083b61427ff9724c7706fcf (diff) | |
download | spike-plic_uart_v1.zip spike-plic_uart_v1.tar.gz spike-plic_uart_v1.tar.bz2 |
Merge branch 'master' into plic_uart_v1plic_uart_v1
Diffstat (limited to 'riscv/insns/vrgather_vi.h')
-rw-r--r-- | riscv/insns/vrgather_vi.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/riscv/insns/vrgather_vi.h b/riscv/insns/vrgather_vi.h index 56e11e1..85ba621 100644 --- a/riscv/insns/vrgather_vi.h +++ b/riscv/insns/vrgather_vi.h @@ -7,10 +7,6 @@ require_vm; reg_t zimm5 = insn.v_zimm5(); VI_LOOP_BASE - -for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { - VI_LOOP_ELEMENT_SKIP(); - switch (sew) { case e8: P.VU.elt<uint8_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, zimm5); @@ -25,6 +21,4 @@ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { P.VU.elt<uint64_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, zimm5); break; } -} - VI_LOOP_END; |