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| author | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
| commit | 68aeeb5500521ff52c216862f9a653b64191f3ad (patch) | |
| tree | 407230ff48f79f177a792451598d9b2b6e3d34a0 /riscv/insns/vrem_vv.h | |
| parent | 191634d2854dfed448fc323195f9b65c305e2d77 (diff) | |
| parent | 03be4ae6c7b8e9865083b61427ff9724c7706fcf (diff) | |
| download | spike-plic_uart_v1.zip spike-plic_uart_v1.tar.gz spike-plic_uart_v1.tar.bz2 | |
Merge branch 'master' into plic_uart_v1plic_uart_v1
Diffstat (limited to 'riscv/insns/vrem_vv.h')
| -rw-r--r-- | riscv/insns/vrem_vv.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vrem_vv.h b/riscv/insns/vrem_vv.h index 260716a..5c58fa4 100644 --- a/riscv/insns/vrem_vv.h +++ b/riscv/insns/vrem_vv.h @@ -3,7 +3,7 @@ VI_VV_LOOP ({ if (vs1 == 0) vd = vs2; - else if(vs2 == -(((intmax_t)1) << (sew - 1)) && vs1 == -1) + else if (vs2 == -(((intmax_t)1) << (sew - 1)) && vs1 == -1) vd = 0; else { vd = vs2 % vs1; |