diff options
| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-27 19:35:45 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-28 22:59:58 -0700 |
| commit | 09adc65e7db92c651b26e376b964efec585cc268 (patch) | |
| tree | 1e9b71f361da8ed0616ae81fc722c25c1312b72b /riscv/insns/vmsif_m.h | |
| parent | 1bf9d025f7efaf153d551a1128d423444522ba3f (diff) | |
| download | spike-09adc65e7db92c651b26e376b964efec585cc268.zip spike-09adc65e7db92c651b26e376b964efec585cc268.tar.gz spike-09adc65e7db92c651b26e376b964efec585cc268.tar.bz2 | |
rvv: apply new overlapping and align macro
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vmsif_m.h')
| -rw-r--r-- | riscv/insns/vmsif_m.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/riscv/insns/vmsif_m.h b/riscv/insns/vmsif_m.h index bbdadf3..73aadbc 100644 --- a/riscv/insns/vmsif_m.h +++ b/riscv/insns/vmsif_m.h @@ -2,10 +2,11 @@ require(P.VU.vsew >= e8 && P.VU.vsew <= e64); require_vector; require(P.VU.vstart == 0); +if (insn.v_vm() == 0) + require(insn.rd() != 0 && insn.rd() != insn.rs2()); + reg_t vl = P.VU.vl; -reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); -reg_t rs1_num = insn.rs1(); reg_t rs2_num = insn.rs2(); bool has_one = false; |