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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-25 00:11:48 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-25 00:11:48 -0700 |
| commit | ba69781e5d2bdafc5f8356e246c56261ec838729 (patch) | |
| tree | 1f8c0a7b6b5a53f0fab196125fcb57269aedd34f /riscv/insns/vl1r_v.h | |
| parent | a878edfef23ca7deb3c0698e8c9b1d674ba86cf0 (diff) | |
| download | spike-ba69781e5d2bdafc5f8356e246c56261ec838729.zip spike-ba69781e5d2bdafc5f8356e246c56261ec838729.tar.gz spike-ba69781e5d2bdafc5f8356e246c56261ec838729.tar.bz2 | |
rvv: fix wrong vill checking
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vl1r_v.h')
| -rw-r--r-- | riscv/insns/vl1r_v.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vl1r_v.h b/riscv/insns/vl1r_v.h index 09f4040..61e8765 100644 --- a/riscv/insns/vl1r_v.h +++ b/riscv/insns/vl1r_v.h @@ -1,5 +1,5 @@ // vl1r.v vd, (rs1) -require_vector; +require_vector_novtype(true); const reg_t baseAddr = RS1; const reg_t vd = insn.rd(); for (reg_t i = 0; i < P.VU.vlenb; ++i) { |