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authorChih-Min Chao <chihmin.chao@sifive.com>2020-09-10 20:52:33 -0700
committerChih-Min Chao <chihmin.chao@sifive.com>2020-09-22 21:08:54 -0700
commitb8832af2d97f1936c8b813628c2941d22719d736 (patch)
tree75eacb7c0366752cf9cecfaa1de996d0177e20e3 /riscv/insns/vfncvt_rod_f_f_w.h
parent648e16e7783f1a91d7f65b4b8d38a84d917235d6 (diff)
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rvv: fix vfncvt/vfwcvt type checking
for each case, use explicit type checking Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vfncvt_rod_f_f_w.h')
-rw-r--r--riscv/insns/vfncvt_rod_f_f_w.h12
1 files changed, 11 insertions, 1 deletions
diff --git a/riscv/insns/vfncvt_rod_f_f_w.h b/riscv/insns/vfncvt_rod_f_f_w.h
index 11d87e0..7113fd5 100644
--- a/riscv/insns/vfncvt_rod_f_f_w.h
+++ b/riscv/insns/vfncvt_rod_f_f_w.h
@@ -12,4 +12,14 @@ VI_VFP_CVT_SCALE
softfloat_roundingMode = softfloat_round_odd;
auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
P.VU.elt<float32_t>(rd_num, i, true) = f64_to_f32(vs2);
-}, false, (P.VU.vsew >= 16))
+},
+{
+ ;
+},
+{
+ require(p->supports_extension(EXT_ZFH));
+},
+{
+ require(p->supports_extension('F'));
+},
+false, (P.VU.vsew >= 16))