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| author | Scott Johnson <scott.johnson@arilinc.com> | 2020-11-10 22:02:20 -0800 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2020-11-11 09:55:12 -0800 |
| commit | f019910e120874422220d3c5c6a9711cbf574bad (patch) | |
| tree | 5a9e6d6283fed832aded547fd398a1a66baaaf08 /riscv/insns/lr_w.h | |
| parent | 956ef9ac3a66d2d6cda5df33a0e3f1c7d57ed0e0 (diff) | |
| download | spike-f019910e120874422220d3c5c6a9711cbf574bad.zip spike-f019910e120874422220d3c5c6a9711cbf574bad.tar.gz spike-f019910e120874422220d3c5c6a9711cbf574bad.tar.bz2 | |
Make LR properly take misaligned exception
Fixes https://github.com/riscv/riscv-isa-sim/issues/591
Diffstat (limited to 'riscv/insns/lr_w.h')
| -rw-r--r-- | riscv/insns/lr_w.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/lr_w.h b/riscv/insns/lr_w.h index 8605cc5..185be53 100644 --- a/riscv/insns/lr_w.h +++ b/riscv/insns/lr_w.h @@ -1,4 +1,4 @@ require_extension('A'); -auto res = MMU.load_int32(RS1); +auto res = MMU.load_int32(RS1, true); MMU.acquire_load_reservation(RS1); WRITE_RD(res); |