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authorAndrew Waterman <andrew@sifive.com>2020-03-20 01:48:03 -0700
committerAndrew Waterman <andrew@sifive.com>2020-03-20 01:48:58 -0700
commit59a9277ac1e3f9aca630fb035d1dbacaa091e375 (patch)
treec31c933c69e5e3217d88333f4d4fe2c7143ad078 /riscv/insns/ebreak.h
parentf3055afa55125627be0b64bf7b8bd1c876d9bc79 (diff)
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ebreak should write mtval with 0, not pc
Resolves #426 The relevant passage in the spec does not mention software breakpoints as one of the cases that cause mtval to be set to a nonzero value: https://github.com/riscv/riscv-isa-manual/blob/274893e2f0365f904829bbb60fd05cc01d2bfb11/src/machine.tex#L2202
Diffstat (limited to 'riscv/insns/ebreak.h')
-rw-r--r--riscv/insns/ebreak.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/ebreak.h b/riscv/insns/ebreak.h
index 736cebe..c22776c 100644
--- a/riscv/insns/ebreak.h
+++ b/riscv/insns/ebreak.h
@@ -1 +1 @@
-throw trap_breakpoint(pc);
+throw trap_breakpoint();