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authorAndrew Waterman <waterman@cs.berkeley.edu>2015-05-31 16:38:24 -0700
committerAndrew Waterman <waterman@cs.berkeley.edu>2015-05-31 18:29:45 -0700
commit56701b230823f52c252ce6ab69c18639daa02a14 (patch)
tree96935c7b7154db38f675210f94b5dea34bef84f2 /riscv/insns/c_slliw.h
parent5235a77475ff00aecafb9db4c1b003043d2d7f20 (diff)
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Add rest of RV32C instructions
Diffstat (limited to 'riscv/insns/c_slliw.h')
-rw-r--r--riscv/insns/c_slliw.h16
1 files changed, 12 insertions, 4 deletions
diff --git a/riscv/insns/c_slliw.h b/riscv/insns/c_slliw.h
index 87a5901..643bf74 100644
--- a/riscv/insns/c_slliw.h
+++ b/riscv/insns/c_slliw.h
@@ -1,5 +1,13 @@
require_extension('C');
-require_rv64;
-require(insn.rvc_rd() != 0);
-require(insn.rvc_imm() < 32);
-WRITE_RD(sext32(RVC_RS1 << insn.rvc_imm()));
+if (xlen == 32) {
+ switch ((insn.bits() >> 5) & 3) {
+ case 0: WRITE_RVC_RS2S(sext_xlen(RVC_RS1S + insn.rvc_simm3())); // c.addin
+ case 1: WRITE_RVC_RS2S(sext_xlen(RVC_RS1S ^ insn.rvc_simm3())); // c.xorin
+ case 2: WRITE_RVC_RS2S(sext_xlen(RVC_RS1S | insn.rvc_simm3())); // c.orin
+ case 3: WRITE_RVC_RS2S(sext_xlen(RVC_RS1S & insn.rvc_simm3())); // c.andin
+ }
+} else {
+ require(insn.rvc_rd() != 0);
+ require(insn.rvc_imm() < 32);
+ WRITE_RD(sext32(RVC_RS1 << insn.rvc_imm()));
+}