Add debug_mode state bit, rather than overloading dcsr.cause

In the previous scheme, debug-mode software could exit debug mode by
zeroing the dcsr.cause field.  While benign, that behavior is out of
spec.

1 files changed, 3 insertions, 3 deletions

diff --git a/riscv/execute.cc b/riscv/execute.cc
index 54e293d..822d934 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -85,13 +85,13 @@ static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
 
 bool processor_t::slow_path()
 {
-  return debug || state.single_step != state.STEP_NONE || state.dcsr.cause;
+  return debug || state.single_step != state.STEP_NONE || state.debug_mode;
 }
 
 // fetch/decode/execute loop
 void processor_t::step(size_t n)
 {
-  if (state.dcsr.cause == DCSR_CAUSE_NONE) {
+  if (!state.debug_mode) {
     if (halt_request) {
       enter_debug_mode(DCSR_CAUSE_DEBUGINT);
     } // !!!The halt bit in DCSR is deprecated.
@@ -130,7 +130,7 @@ void processor_t::step(size_t n)
         {
           if (unlikely(!state.serialized && state.single_step == state.STEP_STEPPED)) {
             state.single_step = state.STEP_NONE;
-            if (state.dcsr.cause == DCSR_CAUSE_NONE) {
+            if (!state.debug_mode) {
               enter_debug_mode(DCSR_CAUSE_STEP);
               // enter_debug_mode changed state.pc, so we can't just continue.
               break;