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| author | Tim Newsome <tim@sifive.com> | 2022-03-18 10:11:14 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-04-05 10:10:03 -0700 |
| commit | f2646bf1fb2a40d9a723f8c32078d971a17dba7b (patch) | |
| tree | 00bd3c5f46b16d16b30c480f256adb76f653d45b /riscv/execute.cc | |
| parent | f9c90d729bd9d5772a2a3a320da094d6426911cf (diff) | |
| download | spike-f2646bf1fb2a40d9a723f8c32078d971a17dba7b.zip spike-f2646bf1fb2a40d9a723f8c32078d971a17dba7b.tar.gz spike-f2646bf1fb2a40d9a723f8c32078d971a17dba7b.tar.bz2 | |
trigger_matched_t -> triggers::matched_t
Diffstat (limited to 'riscv/execute.cc')
| -rw-r--r-- | riscv/execute.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index ed03c0d..c57ca3d 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -309,7 +309,7 @@ void processor_t::step(size_t n) enter_debug_mode(DCSR_CAUSE_STEP); } } - catch (trigger_matched_t& t) + catch (triggers::matched_t& t) { if (mmu->matched_trigger) { // This exception came from the MMU. That means the instruction hasn't |