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| author | Andrew Waterman <andrew@sifive.com> | 2022-09-22 17:34:33 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-04 15:40:01 -0700 |
| commit | ce69fb5db97ecf240336b7826dd9dddeb32e5dca (patch) | |
| tree | f78647d0eafa9abc414f5ded2a3663c7506cfd9c /riscv/execute.cc | |
| parent | a51e44ed228e48fc1dbf24ec7dc23cbd61a7874a (diff) | |
| download | spike-ce69fb5db97ecf240336b7826dd9dddeb32e5dca.zip spike-ce69fb5db97ecf240336b7826dd9dddeb32e5dca.tar.gz spike-ce69fb5db97ecf240336b7826dd9dddeb32e5dca.tar.bz2 | |
Suppress most unused variable warnings
Diffstat (limited to 'riscv/execute.cc')
| -rw-r--r-- | riscv/execute.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 36621ca..5d24ce8 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -156,7 +156,7 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) } #endif -inline void processor_t::update_histogram(reg_t pc) +inline void processor_t::update_histogram(reg_t UNUSED pc) { #ifdef RISCV_ENABLE_HISTOGRAM pc_histogram[pc]++; |