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authorAndrew Waterman <andrew@sifive.com>2019-07-12 11:55:01 -0700
committerAndrew Waterman <andrew@sifive.com>2019-07-12 11:55:01 -0700
commitcc6e8787edd5112f3f4476b56022fffc98b2f3be (patch)
tree6dea8df996c56b7d971bbd10ad312fe84ac48835 /riscv/execute.cc
parentee3ef2b189227ee84b33ef69e5c7e9897fea6ba4 (diff)
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Add debug_mode state bit, rather than overloading dcsr.cause
In the previous scheme, debug-mode software could exit debug mode by zeroing the dcsr.cause field. While benign, that behavior is out of spec.
Diffstat (limited to 'riscv/execute.cc')
-rw-r--r--riscv/execute.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc
index 54e293d..822d934 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -85,13 +85,13 @@ static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
bool processor_t::slow_path()
{
- return debug || state.single_step != state.STEP_NONE || state.dcsr.cause;
+ return debug || state.single_step != state.STEP_NONE || state.debug_mode;
}
// fetch/decode/execute loop
void processor_t::step(size_t n)
{
- if (state.dcsr.cause == DCSR_CAUSE_NONE) {
+ if (!state.debug_mode) {
if (halt_request) {
enter_debug_mode(DCSR_CAUSE_DEBUGINT);
} // !!!The halt bit in DCSR is deprecated.
@@ -130,7 +130,7 @@ void processor_t::step(size_t n)
{
if (unlikely(!state.serialized && state.single_step == state.STEP_STEPPED)) {
state.single_step = state.STEP_NONE;
- if (state.dcsr.cause == DCSR_CAUSE_NONE) {
+ if (!state.debug_mode) {
enter_debug_mode(DCSR_CAUSE_STEP);
// enter_debug_mode changed state.pc, so we can't just continue.
break;