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| author | Anup Patel <anup.patel@wdc.com> | 2020-06-21 19:32:09 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-07-08 16:54:00 +0530 |
| commit | b6038de3fcd71703732995bb90bd7d411d330890 (patch) | |
| tree | 567325c30d07a2328432b6015adc5b108ff7b81f /riscv/execute.cc | |
| parent | 89d2591f1b84e7755c0f46166d9e0d6ec0fe7c03 (diff) | |
| download | spike-b6038de3fcd71703732995bb90bd7d411d330890.zip spike-b6038de3fcd71703732995bb90bd7d411d330890.tar.gz spike-b6038de3fcd71703732995bb90bd7d411d330890.tar.bz2 | |
Extend trap classes to pass more information
With hypervisor extension, we have more CSRs providing trap
related information. We extend existing trap classes to pass
additional trap information required by hypervisor extension.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'riscv/execute.cc')
| -rw-r--r-- | riscv/execute.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 4ed2753..a6c7f10 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -347,7 +347,7 @@ void processor_t::step(size_t n) enter_debug_mode(DCSR_CAUSE_HWBP); break; case ACTION_DEBUG_EXCEPTION: { - mem_trap_t trap(CAUSE_BREAKPOINT, t.address); + insn_trap_t trap(CAUSE_BREAKPOINT, t.address); take_trap(trap, pc); break; } |