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authorTim Newsome <tim@sifive.com>2022-05-19 17:11:07 -0700
committerGitHub <noreply@github.com>2022-05-19 17:11:07 -0700
commita0298a33e7b2091ba8d9f3a20838d96dc1164cac (patch)
treef6227ea4d52123b92c7236616317fbba149e2733 /riscv/execute.cc
parent32eeb5a2b2ba6960f3379b23fa41b67ad0a4e38b (diff)
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Move ebreak* logic from take_trap into instructions. (#1006)
Now that logic only affects ebreak instructions, and does not affect triggers that also cause a trap to be taken. Fixes #725. Although like Paul, I don't have a test for this case. Introduce trap_debug_mode so so ebreak instructions can force entry into debug mode.
Diffstat (limited to 'riscv/execute.cc')
-rw-r--r--riscv/execute.cc4
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc
index a6ea7a4..ea4dc5b 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -337,6 +337,10 @@ void processor_t::step(size_t n)
abort();
}
}
+ catch(trap_debug_mode&)
+ {
+ enter_debug_mode(DCSR_CAUSE_SWBP);
+ }
catch (wait_for_interrupt_t &t)
{
// Return to the outer simulation loop, which gives other devices/harts a