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| author | Tim Newsome <tim@sifive.com> | 2020-05-26 14:57:07 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-26 14:57:07 -0700 |
| commit | 88c87dbbcf508b78ee2272528f5d404f3e5a0796 (patch) | |
| tree | 9359fa1e7b60d4dc181bb5310d7f38666508fe10 /riscv/execute.cc | |
| parent | b7c09621ea87e99cca42da307e461707c6e7cbf1 (diff) | |
| download | spike-88c87dbbcf508b78ee2272528f5d404f3e5a0796.zip spike-88c87dbbcf508b78ee2272528f5d404f3e5a0796.tar.gz spike-88c87dbbcf508b78ee2272528f5d404f3e5a0796.tar.bz2 | |
Report haltgroup halt cause, per the debug spec. (#473)
Diffstat (limited to 'riscv/execute.cc')
| -rw-r--r-- | riscv/execute.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index b4ffc4c..6f484c5 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -196,8 +196,10 @@ bool processor_t::slow_path() void processor_t::step(size_t n) { if (!state.debug_mode) { - if (halt_request) { + if (halt_request == HR_REGULAR) { enter_debug_mode(DCSR_CAUSE_DEBUGINT); + } else if (halt_request == HR_GROUP) { + enter_debug_mode(DCSR_CAUSE_GROUP); } // !!!The halt bit in DCSR is deprecated. else if (state.dcsr.halt) { enter_debug_mode(DCSR_CAUSE_HALT); |