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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-01 22:34:58 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-02 21:42:30 -0700 |
| commit | 580ef6a6a519ea40d2680eed26d3c6e75bf4f763 (patch) | |
| tree | 992b44b2e301f93e7a2c760ba8a338828b1d0c4b /riscv/execute.cc | |
| parent | 0fefb0cf6de06f5ee625cff59cecb42ae9ae3b55 (diff) | |
| download | spike-580ef6a6a519ea40d2680eed26d3c6e75bf4f763.zip spike-580ef6a6a519ea40d2680eed26d3c6e75bf4f763.tar.gz spike-580ef6a6a519ea40d2680eed26d3c6e75bf4f763.tar.bz2 | |
commitlog: support csr access
For csr register access instructions, there are log like
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/execute.cc')
| -rw-r--r-- | riscv/execute.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index f907591..4ed2753 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -2,6 +2,7 @@ #include "processor.h" #include "mmu.h" +#include "disasm.h" #include <cassert> #ifdef RISCV_ENABLE_COMMITLOG @@ -121,7 +122,10 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) } if (!is_vec) { - fprintf(log_file, " %c%2d ", prefix, rd); + if (prefix == 'c') + fprintf(log_file, " c%d_%s ", rd, csr_name(rd)); + else + fprintf(log_file, " %c%2d ", prefix, rd); if (is_vreg) commit_log_print_value(log_file, size, &p->VU.elt<uint8_t>(rd, 0)); else |