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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-02 00:03:17 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-02 21:24:19 -0700 |
| commit | 3e9c9f75e9720ce5ce2c2b41e5defd9dad9d4915 (patch) | |
| tree | d6d0d7aa29cc5966c3afead8b21e3bca5c9cb1ee /riscv/execute.cc | |
| parent | 0884e5bbd77a4df950c2ccfff78ad157ffcec631 (diff) | |
| download | spike-3e9c9f75e9720ce5ce2c2b41e5defd9dad9d4915.zip spike-3e9c9f75e9720ce5ce2c2b41e5defd9dad9d4915.tar.gz spike-3e9c9f75e9720ce5ce2c2b41e5defd9dad9d4915.tar.bz2 | |
commitlog: extend hint bit to record csr access
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/execute.cc')
| -rw-r--r-- | riscv/execute.cc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 7e89cd1..45fa516 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -81,10 +81,10 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) char prefix; int size; - int rd = item.first >> 2; + int rd = item.first >> 4; bool is_vec = false; bool is_vreg = false; - switch (item.first & 3) { + switch (item.first & 0xf) { case 0: size = xlen; prefix = 'x'; @@ -101,6 +101,10 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) case 3: is_vec = true; break; + case 4: + size = xlen; + prefix = 'c'; + break; default: assert("can't been here" && 0); break; |