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| author | Tim Newsome <tim@sifive.com> | 2022-03-15 10:41:21 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-03-30 10:41:44 -0700 |
| commit | 16ed520e8d35a0eaa56b708aa540400312acdc09 (patch) | |
| tree | 967ea7845312a56a265e37c141d5ad5f2dc0b028 /riscv/execute.cc | |
| parent | beaf1601e065f1399c9e2b12c48bbb713a8c40c3 (diff) | |
| download | spike-16ed520e8d35a0eaa56b708aa540400312acdc09.zip spike-16ed520e8d35a0eaa56b708aa540400312acdc09.tar.gz spike-16ed520e8d35a0eaa56b708aa540400312acdc09.tar.bz2 | |
Replace state.mcontrol with TM.triggers.
Created a new triggers::module_t to hold the structure.
Also make sure mcontrol_t instances are properly initialized.
Diffstat (limited to 'riscv/execute.cc')
| -rw-r--r-- | riscv/execute.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 212f273..ed03c0d 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -324,7 +324,7 @@ void processor_t::step(size_t n) delete mmu->matched_trigger; mmu->matched_trigger = NULL; } - switch (state.mcontrol[t.index].action) { + switch (TM.triggers[t.index]->action) { case triggers::ACTION_DEBUG_MODE: enter_debug_mode(DCSR_CAUSE_HWBP); break; |