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| author | Andrew Waterman <andrew@sifive.com> | 2017-02-20 18:48:35 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-02-20 18:48:35 -0800 |
| commit | 13639b9c457b3879efa620ce55abddbdc834ce68 (patch) | |
| tree | 4d8705117cf62d23067f042b663b5d020f8e6dbf /riscv/execute.cc | |
| parent | b47e8c0a190ac17d2622d5554b21bc871d56847a (diff) | |
| download | spike-13639b9c457b3879efa620ce55abddbdc834ce68.zip spike-13639b9c457b3879efa620ce55abddbdc834ce68.tar.gz spike-13639b9c457b3879efa620ce55abddbdc834ce68.tar.bz2 | |
serialize simulator on wfi
This improves simulator perf when a thread is idle, or waiting on HTIF.
Diffstat (limited to 'riscv/execute.cc')
| -rw-r--r-- | riscv/execute.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index ebc9dc7..1b53ccf 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -84,7 +84,7 @@ void processor_t::step(size_t n) if (unlikely(invalid_pc(pc))) { \ switch (pc) { \ case PC_SERIALIZE_BEFORE: state.serialized = true; break; \ - case PC_SERIALIZE_AFTER: instret++; break; \ + case PC_SERIALIZE_AFTER: n = ++instret; break; \ default: abort(); \ } \ pc = state.pc; \ |