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| author | Tim Newsome <tim@sifive.com> | 2016-05-23 16:17:28 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 16:17:28 -0700 |
| commit | 968408423f8d45deaa12a5c0cf9fc729f2efe38a (patch) | |
| tree | 25db0a603e8d6d50519de0b03ec26e73b5867661 /riscv/encoding.h | |
| parent | cfdd0f22f6b7c27280ff73722eb35a8f9af7c54b (diff) | |
| download | spike-968408423f8d45deaa12a5c0cf9fc729f2efe38a.zip spike-968408423f8d45deaa12a5c0cf9fc729f2efe38a.tar.gz spike-968408423f8d45deaa12a5c0cf9fc729f2efe38a.tar.bz2 | |
Change DCSR bits to match spec.
Cleaned up debug ROM code a little.
Diffstat (limited to 'riscv/encoding.h')
| -rw-r--r-- | riscv/encoding.h | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index e3371af..0f1926a 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -33,21 +33,21 @@ #define SSTATUS32_SD 0x80000000 #define SSTATUS64_SD 0x8000000000000000 -#define DCSR_XDEBUGVER (3<<29) -#define DCSR_HWBPCOUNT (0xfff<<17) -#define DCSR_PRV (3<<14) -#define DCSR_NDRESET (1<<13) -#define DCSR_FULLRESET (1<<12) -#define DCSR_STEP (1<<11) -#define DCSR_DEBUGINT (1<<10) -#define DCSR_STOPCYCLE (1<<9) -#define DCSR_STOPTIME (1<<8) -#define DCSR_EBREAKM (1<<7) -#define DCSR_EBREAKH (1<<6) -#define DCSR_EBREAKS (1<<5) -#define DCSR_EBREAKU (1<<4) +#define DCSR_XDEBUGVER (3<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_HWBPCOUNT (0xfff<<16) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) #define DCSR_HALT (1<<3) -#define DCSR_CAUSE 7 +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) #define DCSR_CAUSE_NONE 0 #define DCSR_CAUSE_SWBP 1 |