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| author | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-22 13:57:56 -0700 |
|---|---|---|
| committer | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-22 14:21:54 -0700 |
| commit | 46f1423c6566aee512fbc7a8ef6ff4aae2b7d1fb (patch) | |
| tree | 1ff563929c13be279340ad439af8692d3c9913aa /riscv/encoding.h | |
| parent | 693fc45eb8ccc3c9f84b898de3119a172e0776f5 (diff) | |
| download | spike-46f1423c6566aee512fbc7a8ef6ff4aae2b7d1fb.zip spike-46f1423c6566aee512fbc7a8ef6ff4aae2b7d1fb.tar.gz spike-46f1423c6566aee512fbc7a8ef6ff4aae2b7d1fb.tar.bz2 | |
riscv: replace rtc device with a real clint implementation
Diffstat (limited to 'riscv/encoding.h')
| -rw-r--r-- | riscv/encoding.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index ef68c2f..3923bff 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -137,6 +137,8 @@ #define IRQ_HOST 13 #define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 #define EXT_IO_BASE 0x40000000 #define DRAM_BASE 0x80000000 |