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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-20 00:48:16 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-20 00:48:16 -0700 |
| commit | ee80f2851aef29f8744b5a73afe45a1927c82b37 (patch) | |
| tree | 3876cd72a36b225c8fc665e8469f5e5d49dc0081 /riscv/encoding.h | |
| parent | 5ed1c1f9de8053ff99e3568c2ed3957da21ce0c5 (diff) | |
| download | spike-ee80f2851aef29f8744b5a73afe45a1927c82b37.zip spike-ee80f2851aef29f8744b5a73afe45a1927c82b37.tar.gz spike-ee80f2851aef29f8744b5a73afe45a1927c82b37.tar.bz2 | |
PUM -> SUM; expose MXR to S-mode
Diffstat (limited to 'riscv/encoding.h')
| -rw-r--r-- | riscv/encoding.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index 1b9883e..60ee674 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -17,7 +17,7 @@ #define MSTATUS_FS 0x00006000 #define MSTATUS_XS 0x00018000 #define MSTATUS_MPRV 0x00020000 -#define MSTATUS_PUM 0x00040000 +#define MSTATUS_SUM 0x00040000 #define MSTATUS_MXR 0x00080000 #define MSTATUS_TVM 0x00100000 #define MSTATUS_TW 0x00200000 @@ -32,7 +32,8 @@ #define SSTATUS_SPP 0x00000100 #define SSTATUS_FS 0x00006000 #define SSTATUS_XS 0x00018000 -#define SSTATUS_PUM 0x00040000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 #define SSTATUS32_SD 0x80000000 #define SSTATUS64_SD 0x8000000000000000 |