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author | Ben Marshall <ben.marshall@bristol.ac.uk> | 2021-02-18 13:27:35 +0000 |
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committer | Ben Marshall <ben.marshall@bristol.ac.uk> | 2021-02-18 13:27:35 +0000 |
commit | da7748e6d88c75559e8f3c09067a502fe950136e (patch) | |
tree | a0d7a9151682bdc4f26431c79624fef6c8957fbc /riscv/encoding.h | |
parent | 5730d12167e0a0834d14b6332a4dd31d673bf73b (diff) | |
download | spike-da7748e6d88c75559e8f3c09067a502fe950136e.zip spike-da7748e6d88c75559e8f3c09067a502fe950136e.tar.gz spike-da7748e6d88c75559e8f3c09067a502fe950136e.tar.bz2 |
scalar-crypto: Fix decoding of RV64 AES instructions.
Historically, one could uniquely decode any RISC-V instruction based on
the instruciton to decode, plus a MATCH and MASK pair.
The scalar crypto extension adds instructions for accelerating the AES
algorithm which work very differently on RV32 and RV64. However, they
overlap in terms of opcodes. The instructions are always mutually
exclusive, and so it makes sense to overlap them this way to save
encoding space.
This exposed a problem, where previously Spike assumed the decoder
function was something like:
> decode(instr_word, MATCH, MASK)
Now it needed to be
> decode(instr_word, MATCH, MASK, current_xlen)
To get around this in the initial implementation, the instructions which
shared opcodes were implemented in the same *.h file - e.g. aesds.h
contained an implementation of aes32dsi, and aes64ds. We detected
xlen in the file, and executed the appropriate instruction logic.
This worked fine for our limited set of benchmarks.
After more extensive testing, we found that Spike has an optimisation
which changes the order in which it tries to decode instructions based
on past instructions.
Running more extensive tests exposed the fact that the decoding logic
could still not unambiguously decode the instructions. Hence, more
substantial changes were needed to tell spike that an instruction is
RV32 or RV64 only.
These changes have been implemented as part of
- riscv/encoding.h
- disasm/disasm.cc
- riscv/processor.cc/h
Basically, every instr_desc_t has an extra field which marks which
base architecture the instruction can be exectuted on. This bitfield
can be altered for particular instructions.
The changes to riscv/insns/* simply split out the previously combined
instructions into a separate header files.
On branch scalar-crypto-fix
Changes to be committed:
modified: disasm/disasm.cc
modified: riscv/encoding.h
new file: riscv/insns/aes32dsi.h
new file: riscv/insns/aes32dsmi.h
new file: riscv/insns/aes32esi.h
new file: riscv/insns/aes32esmi.h
new file: riscv/insns/aes64ds.h
new file: riscv/insns/aes64dsm.h
new file: riscv/insns/aes64es.h
new file: riscv/insns/aes64esm.h
deleted: riscv/insns/aesds.h
deleted: riscv/insns/aesdsm.h
deleted: riscv/insns/aeses.h
deleted: riscv/insns/aesesm.h
modified: riscv/processor.cc
modified: riscv/processor.h
modified: riscv/riscv.mk.in
Diffstat (limited to 'riscv/encoding.h')
-rw-r--r-- | riscv/encoding.h | 63 |
1 files changed, 51 insertions, 12 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index 160dc29..eb0c49b 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -967,14 +967,28 @@ #define MATCH_AES64IM 0x30001013 #define MASK_AES64KS2 0xfe00707f #define MATCH_AES64KS2 0x7e000033 -#define MASK_AESESM 0x3e00707f -#define MATCH_AESESM 0x36000033 -#define MASK_AESES 0x3e00707f -#define MATCH_AESES 0x32000033 -#define MASK_AESDSM 0x3e00707f -#define MATCH_AESDSM 0x3e000033 -#define MASK_AESDS 0x3e00707f -#define MATCH_AESDS 0x3a000033 +#define MASK_AES32ESMI 0x3e007fff +#define MATCH_AES32ESMI 0x36000033 +#define MASK_AES32ESI 0x3e007fff +#define MATCH_AES32ESI 0x32000033 +#define MASK_AES32DSMI 0x3e007fff +#define MATCH_AES32DSMI 0x3e000033 +#define MASK_AES32DSI 0x3e007fff +#define MATCH_AES32DSI 0x3a000033 +#define MASK_AES64KS1I 0xff00707f +#define MATCH_AES64KS1I 0x31001013 +#define MASK_AES64IM 0xfff0707f +#define MATCH_AES64IM 0x30001013 +#define MASK_AES64KS2 0xfe00707f +#define MATCH_AES64KS2 0x7e000033 +#define MASK_AES64ESM 0xfe00707f +#define MATCH_AES64ESM 0x36000033 +#define MASK_AES64ES 0xfe00707f +#define MATCH_AES64ES 0x32000033 +#define MASK_AES64DSM 0xfe00707f +#define MATCH_AES64DSM 0x3e000033 +#define MASK_AES64DS 0xfe00707f +#define MATCH_AES64DS 0x3a000033 #define MASK_SHA512SUM0 0xfff0707f #define MATCH_SHA512SUM0 0x10401013 #define MASK_SHA512SUM1 0xfff0707f @@ -2746,10 +2760,25 @@ DECLARE_INSN(sm4ks, MATCH_SM4KS, MASK_SM4KS) DECLARE_INSN(aes64ks1i, MATCH_AES64KS1I, MASK_AES64KS1I) DECLARE_INSN(aes64ks2, MATCH_AES64KS2, MASK_AES64KS2) DECLARE_INSN(aes64im, MATCH_AES64IM, MASK_AES64IM) -DECLARE_INSN(aesesm, MATCH_AESESM, MASK_AESESM) -DECLARE_INSN(aeses, MATCH_AESES, MASK_AESES) -DECLARE_INSN(aesdsm, MATCH_AESDSM, MASK_AESDSM) -DECLARE_INSN(aesds, MATCH_AESDS, MASK_AESDS) +DECLARE_INSN(aes64es, MATCH_AES64ES, MASK_AES64ES) +DECLARE_INSN(aes64esm, MATCH_AES64ESM, MASK_AES64ESM) +DECLARE_INSN(aes64ds, MATCH_AES64DS, MASK_AES64DS) +DECLARE_INSN(aes64dsm, MATCH_AES64DSM, MASK_AES64DSM) +DECLARE_RV64_ONLY(aes64ks1i) +DECLARE_RV64_ONLY(aes64ks2) +DECLARE_RV64_ONLY(aes64im) +DECLARE_RV64_ONLY(aes64es) +DECLARE_RV64_ONLY(aes64esm) +DECLARE_RV64_ONLY(aes64ds) +DECLARE_RV64_ONLY(aes64dsm) +DECLARE_INSN(aes32esi, MATCH_AES32ESI, MASK_AES32ESI) +DECLARE_INSN(aes32esmi, MATCH_AES32ESMI, MASK_AES32ESMI) +DECLARE_INSN(aes32dsi, MATCH_AES32DSI, MASK_AES32DSI) +DECLARE_INSN(aes32dsmi, MATCH_AES32DSMI, MASK_AES32DSMI) +DECLARE_RV32_ONLY(aes32esi) +DECLARE_RV32_ONLY(aes32esmi) +DECLARE_RV32_ONLY(aes32dsi) +DECLARE_RV32_ONLY(aes32dsmi) DECLARE_INSN(sha256sig0, MATCH_SHA256SIG0, MASK_SHA256SIG0) DECLARE_INSN(sha256sig1, MATCH_SHA256SIG1, MASK_SHA256SIG1) DECLARE_INSN(sha256sum0, MATCH_SHA256SUM0, MASK_SHA256SUM0) @@ -2762,10 +2791,20 @@ DECLARE_INSN(sha512sig1l, MATCH_SHA512SIG1L, MASK_SHA512SIG1L) DECLARE_INSN(sha512sig1h, MATCH_SHA512SIG1H, MASK_SHA512SIG1H) DECLARE_INSN(sha512sum0r, MATCH_SHA512SUM0R, MASK_SHA512SUM0R) DECLARE_INSN(sha512sum1r, MATCH_SHA512SUM1R, MASK_SHA512SUM1R) +DECLARE_RV32_ONLY(sha512sig0l) +DECLARE_RV32_ONLY(sha512sig0h) +DECLARE_RV32_ONLY(sha512sig1l) +DECLARE_RV32_ONLY(sha512sig1h) +DECLARE_RV32_ONLY(sha512sum0r) +DECLARE_RV32_ONLY(sha512sum1r) DECLARE_INSN(sha512sig0, MATCH_SHA512SIG0, MASK_SHA512SIG0) DECLARE_INSN(sha512sig1, MATCH_SHA512SIG1, MASK_SHA512SIG1) DECLARE_INSN(sha512sum0, MATCH_SHA512SUM0, MASK_SHA512SUM0) DECLARE_INSN(sha512sum1, MATCH_SHA512SUM1, MASK_SHA512SUM1) +DECLARE_RV64_ONLY(sha512sig0) +DECLARE_RV64_ONLY(sha512sig1) +DECLARE_RV64_ONLY(sha512sum0) +DECLARE_RV64_ONLY(sha512sum1) DECLARE_INSN(pollentropy, MATCH_POLLENTROPY, MASK_POLLENTROPY) DECLARE_INSN(getnoise, MATCH_GETNOISE, MASK_GETNOISE) DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) |