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| author | Daniel Lustig <dlustig@nvidia.com> | 2021-07-20 13:30:16 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-07-20 10:30:16 -0700 |
| commit | cb8f09a4d6fed30527fdd832b885c898b4591a5f (patch) | |
| tree | d29859362cdb20f83e57899bacdfad628756c92d /riscv/encoding.h | |
| parent | ec6f7b08ff59929313de1cff90973f34c5747ea9 (diff) | |
| download | spike-cb8f09a4d6fed30527fdd832b885c898b4591a5f.zip spike-cb8f09a4d6fed30527fdd832b885c898b4591a5f.tar.gz spike-cb8f09a4d6fed30527fdd832b885c898b4591a5f.tar.bz2 | |
Priv virtual memory updates (#750)
* Priv virtual memory updates
* Priv 1.12 requires page faults when the address translation process
reaches a PTE with any reserved bit set
* Svpbmt uses two PTE bits, but otherwise has no effect on Spike (since
Spike is sequentially consistent and does not model PMAs)
* Add Svinval instructions
Even though I updated riscv-opcodes separately, I merged the new
defines into riscv/encoding.h manually, because riscv-opcodes seems
to be a step ahead of riscv-isa-sim for a few vector opcodes, causing
conflicts when regenerating encoding.h...
If that gets fixed, and encoding.h gets regenerated automatically, I can
remove it from this PR to avoid conflicts.
* Svinval: use #include rather than copying code
..for the Svinval functions that are implemented in ways that just
mimic SFENCE/HFENCE instructions
Thanks to @aswaterman for the suggestion
Diffstat (limited to 'riscv/encoding.h')
| -rw-r--r-- | riscv/encoding.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index dfc3b75..bde53a4 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -221,7 +221,10 @@ #define PTE_A 0x040 /* Accessed */ #define PTE_D 0x080 /* Dirty */ #define PTE_SOFT 0x300 /* Reserved for Software */ +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */ +#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */ #define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */ +#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */ #define PTE_PPN_SHIFT 10 @@ -1020,6 +1023,16 @@ #define MASK_CSRRSI 0x707f #define MATCH_CSRRCI 0x7073 #define MASK_CSRRCI 0x707f +#define MATCH_SINVAL_VMA 0x16000073 +#define MASK_SINVAL_VMA 0xfe007fff +#define MATCH_SFENCE_W_INVAL 0x18000073 +#define MASK_SFENCE_W_INVAL 0xfff07fff +#define MATCH_SFENCE_INVAL_IR 0x18100073 +#define MASK_SFENCE_INVAL_IR 0xfff07fff +#define MATCH_HINVAL_VVMA 0x36000073 +#define MASK_HINVAL_VVMA 0xfe007fff +#define MATCH_HINVAL_GVMA 0x76000073 +#define MASK_HINVAL_GVMA 0xfe007fff #define MATCH_FADD_H 0x4000053 #define MASK_FADD_H 0xfe00007f #define MATCH_FSUB_H 0xc000053 @@ -3475,6 +3488,11 @@ DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA) +DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL) +DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR) +DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA) +DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA) DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H) DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H) DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H) |