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| author | Anup Patel <anup.patel@wdc.com> | 2020-06-13 15:38:21 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-07-09 23:04:07 +0530 |
| commit | 9af85e39a550ba031e4fe9c1913e275959a9927b (patch) | |
| tree | 40e434e8473c0ef517461a0e2d5add4887a27110 /riscv/encoding.h | |
| parent | b6038de3fcd71703732995bb90bd7d411d330890 (diff) | |
| download | spike-9af85e39a550ba031e4fe9c1913e275959a9927b.zip spike-9af85e39a550ba031e4fe9c1913e275959a9927b.tar.gz spike-9af85e39a550ba031e4fe9c1913e275959a9927b.tar.bz2 | |
Implement hypervisor CSRs read/write
We add newly defined hypervisor CSRs and allow M/HS-mode to access
these CSRs. The MRET, SRET, ECALL and WFI instructions have also
been updated so that virt-to-novirt switch and exception cause is
based on HART virtualization state.
Subsequent patches will implement two-stage page tables, HFENCE
instructions and HSV/HLV instructions.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'riscv/encoding.h')
| -rw-r--r-- | riscv/encoding.h | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index a95af6a..be66895 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -43,6 +43,10 @@ #define SSTATUS_UXL 0x0000000300000000 #define SSTATUS64_SD 0x8000000000000000 +#define SSTATUS_VS_MASK (SSTATUS_SIE | SSTATUS_SPIE | \ + SSTATUS_SPP | SSTATUS_SUM | \ + SSTATUS_MXR | SSTATUS_UXL) + #define HSTATUS_VSXL 0x300000000 #define HSTATUS_VTSR 0x00400000 #define HSTATUS_VTW 0x00200000 @@ -127,14 +131,21 @@ #define MIP_MEIP (1 << IRQ_M_EXT) #define MIP_SGEIP (1 << IRQ_S_GEXT) +#define MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP) +#define MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) +#define MIP_HS_MASK (MIP_VS_MASK | MIP_SGEIP) + +#define MIDELEG_FORCED_MASK MIP_HS_MASK + #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP #define PRV_U 0 #define PRV_S 1 -#define PRV_H 2 #define PRV_M 3 +#define PRV_HS (PRV_S + 1) + #define SATP32_MODE 0x80000000 #define SATP32_ASID 0x7FC00000 #define SATP32_PPN 0x003FFFFF @@ -2071,8 +2082,8 @@ #define CAUSE_MISALIGNED_STORE 0x6 #define CAUSE_STORE_ACCESS 0x7 #define CAUSE_USER_ECALL 0x8 -#define CAUSE_SUPERVISOR_ECALL 0x9 -#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_HYPERVISOR_ECALL 0x9 +#define CAUSE_SUPERVISOR_ECALL 0xa #define CAUSE_MACHINE_ECALL 0xb #define CAUSE_FETCH_PAGE_FAULT 0xc #define CAUSE_LOAD_PAGE_FAULT 0xd |