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| author | Andrew Waterman <andrew@sifive.com> | 2021-07-26 07:13:12 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-07-26 07:13:12 -0700 |
| commit | 5aec3dd51998ed5e99100094facd59d246ed0eca (patch) | |
| tree | 067016ab78400be586d206769b81cd9db286263a /riscv/encoding.h | |
| parent | 39070797c1239dd18d286b500c8c76cc02783c47 (diff) | |
| parent | ffcbc2767f2f243320ca9c2f74f0e682330962cc (diff) | |
| download | spike-5aec3dd51998ed5e99100094facd59d246ed0eca.zip spike-5aec3dd51998ed5e99100094facd59d246ed0eca.tar.gz spike-5aec3dd51998ed5e99100094facd59d246ed0eca.tar.bz2 | |
Merge pull request #754 from chihminchao/clean-vqmac-vdot
decode: op: remove quad related macro and define
Diffstat (limited to 'riscv/encoding.h')
| -rw-r--r-- | riscv/encoding.h | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index bde53a4..39e9aa0 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -1631,8 +1631,6 @@ #define MASK_VFWSUB_WV 0xfc00707f #define MATCH_VFWMUL_VV 0xe0001057 #define MASK_VFWMUL_VV 0xfc00707f -#define MATCH_VFDOT_VV 0xe4001057 -#define MASK_VFDOT_VV 0xfc00707f #define MATCH_VFWMACC_VV 0xf0001057 #define MASK_VFWMACC_VV 0xfc00707f #define MATCH_VFWNMACC_VV 0xf4001057 @@ -1801,16 +1799,6 @@ #define MASK_VWREDSUMU_VS 0xfc00707f #define MATCH_VWREDSUM_VS 0xc4000057 #define MASK_VWREDSUM_VS 0xfc00707f -#define MATCH_VDOTU_VV 0xe0000057 -#define MASK_VDOTU_VV 0xfc00707f -#define MATCH_VDOT_VV 0xe4000057 -#define MASK_VDOT_VV 0xfc00707f -#define MATCH_VQMACCU_VV 0xf0000057 -#define MASK_VQMACCU_VV 0xfc00707f -#define MATCH_VQMACC_VV 0xf4000057 -#define MASK_VQMACC_VV 0xfc00707f -#define MATCH_VQMACCSU_VV 0xfc000057 -#define MASK_VQMACCSU_VV 0xfc00707f #define MATCH_VADD_VI 0x3057 #define MASK_VADD_VI 0xfc00707f #define MATCH_VRSUB_VI 0xc003057 @@ -3792,7 +3780,6 @@ DECLARE_INSN(vfwredosum_vs, MATCH_VFWREDOSUM_VS, MASK_VFWREDOSUM_VS) DECLARE_INSN(vfwadd_wv, MATCH_VFWADD_WV, MASK_VFWADD_WV) DECLARE_INSN(vfwsub_wv, MATCH_VFWSUB_WV, MASK_VFWSUB_WV) DECLARE_INSN(vfwmul_vv, MATCH_VFWMUL_VV, MASK_VFWMUL_VV) -DECLARE_INSN(vfdot_vv, MATCH_VFDOT_VV, MASK_VFDOT_VV) DECLARE_INSN(vfwmacc_vv, MATCH_VFWMACC_VV, MASK_VFWMACC_VV) DECLARE_INSN(vfwnmacc_vv, MATCH_VFWNMACC_VV, MASK_VFWNMACC_VV) DECLARE_INSN(vfwmsac_vv, MATCH_VFWMSAC_VV, MASK_VFWMSAC_VV) @@ -3877,11 +3864,6 @@ DECLARE_INSN(vnclipu_wv, MATCH_VNCLIPU_WV, MASK_VNCLIPU_WV) DECLARE_INSN(vnclip_wv, MATCH_VNCLIP_WV, MASK_VNCLIP_WV) DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS) DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS) -DECLARE_INSN(vdotu_vv, MATCH_VDOTU_VV, MASK_VDOTU_VV) -DECLARE_INSN(vdot_vv, MATCH_VDOT_VV, MASK_VDOT_VV) -DECLARE_INSN(vqmaccu_vv, MATCH_VQMACCU_VV, MASK_VQMACCU_VV) -DECLARE_INSN(vqmacc_vv, MATCH_VQMACC_VV, MASK_VQMACC_VV) -DECLARE_INSN(vqmaccsu_vv, MATCH_VQMACCSU_VV, MASK_VQMACCSU_VV) DECLARE_INSN(vadd_vi, MATCH_VADD_VI, MASK_VADD_VI) DECLARE_INSN(vrsub_vi, MATCH_VRSUB_VI, MASK_VRSUB_VI) DECLARE_INSN(vand_vi, MATCH_VAND_VI, MASK_VAND_VI) |